The technology of integrated circuits has been characterized by a continuing increase in the density with which devices can be formed in a silicon semiconductor chip or substrate. The interconnection of such high density devices requires the formation on the chip surface of conductors that are extremely small and spaced closely together, and conductive patterns that overlap, or, in the terminology of the technology, are vertically spaced at different conductor levels. The use of two or more levels of conductors requires a deposition of a dependable insulation such as silicon dioxide on the lower or first level of conductors of that the overlying upper level or second level can be made without the risk of accidental short circuits or other conductive anomalies.
A favored method for depositing silicon dioxide is known as plasma enhanced chemical vapor deposition (PECVD) in which a ratio-frequency plasma contains a silicon component and an oxygen component. The plasma provides energy for enhancing the reaction required for silicon dioxide formation at temperatures below the melting point of the first level of conductors over which the deposition is made. It should be noted that other oxides such as silicon monoxide may be deposited by this process, but the predominant deposited material is silicon dioxide, which is the term that will be used herein. Also, deposition is on a "substrate," which may be part of the semiconductor, the metal conductors, or previously deposited or grown silicon dioxide.
As circuit density increases, the ratio of the height of adjacent conductors to their separation distance, known as the aspect ratio of the structure, also increases. If the thickness of the deposited silicon dioxide is greater than half the separation between adjacent conductors, the silicon dioxide deposited on adjacent vertical walls of adjacent conductors is likely to meet and cause a discontinuity in the deposited silicon dioxide. If the top corner coverage is slightly greater than the coverage on the remainder of the vertical sidewalls, the corners may meet first, thus producing a void within the deposited silicon dioxide between adjacent conductors. This problem becomes more pressing as the aspect ratio increases.
One solution to the problem is the use of electron cyclotron resonance (ECR) as described, for example, in the paper, "SiO.sub.2 Planarization Technology with Biasing and Electron Cyclotron Resonance Plasma Deposition for Submicron Interconnections," Katsuyuki Machida et al., Journal of Vacuum Science Technology B4 (4), July/August 1986, pp. 818-821. In a chamber connected to the deposition chamber, the combination of an applied microwave frequency and magnetic field sets up a cyclotron resonance of ions which are directed into the deposition chamber and cause silicon dioxide to deposit. The addition of a wafer rf bias in the deposition chamber causes the silicon dioxide to sputter etch, resulting in deposition at different angles on the substrate, thereby to reduce the problem of voids caused by merging vertical walls. One problem with this approach is that it requires the design of new equipment, it is more difficult to maintain the standards of ultracleanliness required in chip manufacture, and the need for microwave and a separate ECR chamber complicate and increase the cost of the apparatus for manufacture.
The paper, "Sidewall-Tapered Oxide by Plasma-Enhanced Chemical Vapor Deposition," G. C. Smith et al., Journal of Electrochemical Society: Solid-State Science and Technology, Vol. 132, No. 11, November 1985, pp. 2721-2725, describes another approach in which sputtering is induced concurrently with silicon dioxide deposition. This leads to V-shaped sidewalls of the deposited silicon dioxide, rather than vertical sidewalls that merge to create voids. A problem with this approach is the relatively long time period required for depositing a useful layer of silicon dioxide over a conductor pattern having a relatively high aspect ratio.
The copending application of Lory et al., Ser. No. 386,650, filed July 31, 1989, describes still another approach to the problem in which an inhibiting gas is use in the plasma that inhibits silicon dioxide deposition on the vertical sidewalls. This gives deposition preferentially on the horizontal features of the structure and prevents voids as long as the aspect ratio is not too high. It works quite well with aspect ratios of lower than 1.0, but, with new circuits, aspect ratios are desired that are as high as 1.7, for which the Lory et al. approach appears to be less than completely reliable.
There is therefore a continuing need in industry for a method for depositing dependable layers of silicon dioxide over conductor patterns having high aspect ratios in a manner that is amenable to mass production, is consistent with cleanliness requirements, and which does not greatly increase the cost of manufacture.